1. Field of the Invention
The present invention relates to a coincidence or identity decision circuit, and more specifically to a coincidence decision circuit composed of field effect transistors (abbreviated "FETs" in this specification).
2. Description of Related Art
Heretofore, the coincidence decision circuit is basically constituted of a combination of logic gates. Referring to FIG. 1, there is shown one typical coincidence decision circuit which includes three input NOR gates 10, 12 and 14 arranged to parallel to each other. One of the input NOR gates 10 is adapted to receive a first coincidence pattern selection signal S.sub.1 and three binary data signals R.sub.1, R.sub.3 and R.sub.5. The second input NOR gate 12 receives a second coincidence pattern selection signal S.sub.2 and three binary data signals R.sub.2, R.sub.3 and R.sub.4. The third input NOR gate 14 receives a third coincidence pattern selection signal S.sub.3 and three binary data signals R.sub.1, R.sub.4 and R.sub.5. Outputs of all the three input NOR gates are connected to an output NOR Gate 16, which generates a coincidence decision output signal "O".
Thus, the coincidence decision circuit shown in FIG. 1 will execute the logic operation expressed by the following formula: EQU O=(S.sub.1 +R.sub.1 +R.sub.3 +R.sub.5).times.(S.sub.2 +R.sub.2 +R.sub.3 +R.sub.4).times.(S.sub.3 +R.sub.1 +R.sub.4 +R.sub.5) (1)
where O, R.sub.i and S.sub.j are logic values of 1 or 0.
In the above coincidence decision circuit, the coincidence pattern selection signals S.sub.1, S.sub.2 and S.sub.3 are such that two or more of the control signals are never simultaneously brought into "0". In this condition, if the coincidence pattern selection signal S.sub.1 is made to "0", the coincidence pattern selection signals S.sub.2 and S.sub.3 are then maintained at "1". Therefore, the outputs of the NOR Gates 12 and 14 are kept at "0". On the other hand, when the train of the data signals (R.sub.1 to R.sub.5)=0, X, 0, X, 0) (where x=arbitrary value), the NOR gate 10 outputs "1", with the result that the output "O" of the NOR gate 16 becomes "0". If the data signal train assumes other combinations of signals, the ouptut of the NOR gate 10 is maintained at "0" and so, the output "O" is kept at "1". Similarly, in the case of S.sub.2 ="0", the output "O" is brought into "0" only when the data signal train (R.sub.1 to R.sub.5)=(X, 0, 0, 0, X). Further, in the case of S.sub.3 ="0", the output "O" is put at "0" only when the data signal train (R.sub.1 to R.sub.5)=(0, X, X, 0, 0).
Namely, when the data signal train (R.sub.1 to R5) is consistent with a specific pattern designated by the coincidence pattern selection signal S.sub.j (j=1 to 3), the coincidence decision output "O" becomes "0". Otherwise, the decision output "O" is maintained at "1".
As mentioned above, conventional coincidence circuits have been constructed to peform the logical function expressed by the logical formula (1) mentioned above or similar logical functions, and have been widely used as general purpose coincidence decision circuits. Here, examining the coincidence circuit shown in FIG. 1, the number "1" of the specifically designated patterns is 3, and the number "m" of the data signals examined for coincidence decision is 3. In addition, the bit number "n" of the selection signals designating each specific pattern is 1. Under this condition, if the respective NOR gates shown in FIG. 1 are constituted of so-called CMOS logic gates, the number of required FETs is as follows: EQU 2.times.1 (m+n+1)=2.times.3(3+1+1)=30
Similarly, in the case of 1=10, m=5, and n=1, if a coincidence circuit is constituted in a manner similar to that of the circuit shown in FIG. 1, the coincidence circuit needs 140 FETs.
As mentioned above, the conventional general purpose coincidence decision circuits require a large number of FETs, and therefore, a power consumption is large. In addition, when the circuits are assembled in integrated circuits, a large chip area is required, and interconnection wiring is complicated.